A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having device characteristics improved by straining the surface of an active region by an isolation insulating layer of a shallow trench isolation (STI) structure and its manufacture method.
B) Description of the Related Art
In a semiconductor device having an STI structure, the shallow trench is filled with an insulating film formed by chemical vapor deposition (CVD) using high density plasma. Thereafter, an unnecessary insulating film is removed by chemical mechanical polishing (CMP). Compressive strain exists in a silicon oxide film deposited by CVD using high density plasma. Strain is therefore generated on the semiconductor surface in an active region. As a gate width becomes narrow, it is not possible to neglect strain caused by the stress applied to the semiconductor surface in an active region. Especially, as the gate width becomes 0.5 μm or narrower, a reduction tendency of an on-state current becomes remarkable due to strain in the channel region.
A relation between strain in a channel region of MOSFET and an amount of drain current change is disclosed in “Evaluation of change in drain current due to strain in 0.13-micrometer-node MOSFETs” by Y. Kumagai et al., Extended Abstract of the 2002 International Conference on SSDM, pp. 14-15. JP-A-P-2004-311954 discloses techniques of improving the characteristics of MOSFET by forming a strain Si layer on an SiGe layer. In this MOSFET, stress is reduced by making corners of STI structure round.